System level modeling of Networks-on-Chip for power estimation and design space exploration

With a fast rising productivity and even faster rising integration densities, i.e., designproductivity-gap, energy and power dissipation are critical topics in high level system design more than ever. Thermal aware system design, reliable power delivery, and the overall energy dissipation are only few crucial design properties. In this work we present a framework based on SystemC, enabling the modeling and simulation of many-core systems reverting to Networks-on-Chip as their communicational infrastructure. The transaction level communication model is clock cycle accurate, yielding a fast yet concise functional simulation. The framework is enriched by parameters concerning technology node and floorplanning and by a thermal model of the eventual chip. Thereby, power estimation and on-chip temperature distribution can be evaluated in an early design phase. Furthermore, the framework is supplemented by extensions enabling an extensive and detailed design space exploration, namely proactive thermal management and thermal aware task mapping.